Integrated circuit memory devices are widely used in consumer and commercial electronics. Integrated circuit memory devices generally include a memory cell array and peripheral circuits for reading data from and writing data to a memory cell array. During and/or as a result of the fabrication process, faults in memory cells of a memory array may occur, including complete failure of the memory cells, failure of particular cells, and failure only under limited circumstances.
Various test mechanisms have been devised to search for and/or identify these and other faults. One known mechanism is a direct access test (DAT), in which the memory allows external test circuitry to directly read from and write to specific memory cells. A direct access test can be implemented by writing data test patterns to memory cells and then reading from the same memory cells. The data written to the memory cells is compared to the data read back to determine the condition of the memory cells. A difference between the data test pattern written to the cells versus the data test pattern read from the cells may indicate a faulty cell(s), which may prompt an alert indicating a failure. Such an alert may be in the form of a single bit indication (e.g., “0” signifies a failure, “1” signifies a “pass” condition).
If the contents of a memory array (or cache or other wide data source) are to be read out, such as for diagnostic purposes or for DAT purposes, a problem often encountered with such operations is that the width of the data path available for these test read operations is smaller than the width of the data stored and read out by the memory array. For example, a memory array read operation may be accomplished using 1024 bits per access, but use a test data path of only 64 bits wide. One solution to this problem may be to multiplex the memory array down onto a narrow test bus. That is, control signals can be used to select one of several slices (e.g., units of data) of the memory array to place on the narrow test bus. One problem with this solution includes the complexity in wiring needed to distribute and route the memory array wires across an array of multipexers. Another problem includes providing a non-intuitive allocation of bits to the various slices (e.g., having adjacent bits in the memory array being split apart and distributed among different slices). Adding to the above described problems is the excessive time and/or circuitry needed to check the value of each slice independently or all slices concurrently.
Some solutions have been introduced to help alleviate some of the problems associated with multiplexing the memory array down onto a narrow test bus. One solution is to conditionally drive the slices of the memory array onto a distributed wired-OR, precharged dynamic bus. For a typical static signal, transistors may pull the signal high (e.g., to Vsource) for a complete clock cycle or low (e.g., to ground) for a complete clock cycle depending on what information is to be placed on a bus. In contrast, a dynamic bus implementation may utilize a precharge device that always pulls the signal high (or low) during the first half of the clock cycle. During the second half of the clock cycle, a transistor may be conditionally turned on, causing the signal to either remain at the current state or change state. A dynamic bus enables a wired-OR bus configuration (unlike static signal designs). With a wired-OR configuration, control signals can select one of several slices of the memory array to be able to discharge the dynamic bus. Further, a dynamic bus can be discharged at any physical location along the dynamic bus. Thus, a conventional dynamic bus enables the collection of data from various slices of an array entry without any explicit multiplexers or the associated wiring congestion. However, a conventional dynamic bus still has disadvantages. For example, DAT testing typically checks the value of each slice independently, which consumes time.